4.2.2Propagation Delay
4.2.3Timing Specifications
4.2.4Sample Timing Specifications
4.2.5Timing Analysis Tools
4.3HDL-Based Digital Design165
4.3.1HDL History
4.3.2Why HDLs?
4.3.3EDA Tool Suites for HDLs
4.3.4HDL-Based Design FlowReferences172
Drill Problems
174Exercises176
5VERILOG HARDWARE DESCRIPTION LANGUAGE177
5.1Verilog Models and Modules179
5.2Logic System, Nets, Variables, and Constants184
5.3Vectors and Operators189
5.4Arrays193
5.5Logical Operators and Expressions194
5.6Compiler Directives197
5.7Structural Models198
5.8Dataflow Models203
5.9Behavioral Models (Procedural Code)205
5.9.1Always Statements and Blocks
5.9.2Procedural Statements
5.9.3Inferred Latches
5.9.4Assignment Statements
5.9.5begin-end Blocks
5.9.6if and if-else Statements
5.9.7case Statements
5.9.8Looping Statements
5.10Functions and Tasks220
5.11The Time Dimension224
5.12Simulation225
5.13Test Benches226
5.14Verilog Features for Sequential Logic Design232
5.15Synthesis232
References233
Drill Problems234
Exercises235
6BASIC COMBINATIONAL LOGICELEMENTS237
6.1Read-Only Memories (ROMs)240
6.1.1ROMs and Truth Tables
6.1.2Using ROMs for Arbitrary Combinational Logic Functions
6.1.3FPGA Lookup Tables (LUTs)
6.2Combinational PLDs246
6.2.1Programmable Logic Arrays
6.2.2Programmable Array Logic Devices
6.3Decoding and Selecti

机械工业出版社国外电子与电气工程技术丛书数字设计:原理与实践(英文版)(第5版)/[美]约翰.F.韦克利 作者简介

约翰·F. 韦克利（John F. Wakerly） 于斯坦福大学获得电子工程博士学位。他目前是思科系统公司广域网业务部主管工程项目的副总裁，还是斯坦福大学的兼职教授。他在数字设计、微型计算机体系结构、计算机可靠性等方面出版了50多部著作，并在电信与网络领域拥有13项专利。

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